In the present day many approaches are investigated to improve performance of semiconductor devices, including dimensional scaling to reduce overall device dimensions. Additionally, silicon based transistors including planar or three dimensional devices may be modified by the use of additional material such as silicon:germanium alloys (SiGe) or compound semiconductors such as InAs or other 3:5 compound semiconductors. Further attempts to improve device performance include the introduction of strain into a transistor channel to increase carrier mobility.
In the case of N-type metal oxide semiconductor field effect transistors (NMOS), no straightforward process to introduce significant strain in the transistor channel has been achieved. One possible route for fabrication of strained transistor channels in NMOS is the use of a SiGe strain relaxed buffer (SRB) layer. This SRB layer is a layer of relaxed SiGe material. Silicon may then be epitaxially grown on the SRB layer. Because of the lattice mismatch between silicon and SiGe, strain is introduced into the silicon grown on the SRB layer. This approach may be employed, for example, in three dimensional transistors, such as fin-type field effect transistors (finFETs). If a finFET device is subsequently fabricated within this strained Si layer the devices may have improved performance due to increased electron mobility imparted into a transistor channel forming part of the finFET device.
In order to capture the potential improvement in device performance in such finFET devices, care may be useful to ensure proper treatment of sidewalls formed on a fin structure of a finFET or sidewalls formed on a gate structure. For example, during a spacer etch operation to process the finFET device according to known process flow, the silicon fin is to be left intact, so strain within the silicon fin is not relieved in the channel region. In addition, during the etching process to form sidewalls on fin structures, sidewall material deposited on the gate structure is also etched. The pulldown of sidewalls formed on the gate structure is to be kept at an acceptable level or avoided in order to reduce gate loss during processing.
It is with respect to these and other considerations the present disclosure is provided.